riscv-peripheral: Support Core-Local Interrupt Controller (CLIC) RISC-V Privileged Architecture Extensions
#195
Conversation
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Wooohoo! Love to see this, thanks so much :) I'll take a look at your implementation ASAP. |
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Beware that the specification of the CLIC is in flux. So what's in the current spec may change. |
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Ah, the CLIC spec has actually just a few days ago left it up to the implementor to define the MMIO layout that this PR implements. The few platforms that do implement CLIC do use this layout however so I guess it can be useful 😃 Gosh. Let's sit on it a while and see where this goes. The CSR updates have stayed the same and we'll be implementing & testing that behavior anyway. |
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Forgot about this PR! I'm OK with merging in master an implementation that matches the current specification and updating this implementation as the specification changes. |
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OK yeah, that sounds reasonable. I've been writing a journal the last 2 weeks and I was just getting back into working on the real-time system implementing this CLIC starting halfway through next week. I think I can get some update done on this within the next month. |
- smclicconfig - clicintie, clicintip, clicintattr
This fixes an issue with unaligned writes.
- Using 32-bit writes to workaround a possible HW bug
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Closed due to MMIO interface obsolescene. I'll re-open / link to this one once I've got the new CSR API working. |
Specification: https://github.com/riscv/riscv-fast-interrupt/blob/master/clic.adoc
We've made a research prototype hardware implementation of rv32emc + CLIC and have completed preliminary tests showing that this software implementation for CLIC works. However, there's a few open issues:
riscv::register::mcausedynamically allocates a different number of bits forcodedepending on whetherriscv::mtvec::trap_modeis set toClic = 0b11or not.riscv_peripheral::clic::intctldepends on the value set inriscv_peripheral::clic::smclicconfig::mnlbits.clicintxregisters slightly un-ideal.